The present invention relates to a semiconductor device, a mobile communication device, and a method for manufacturing a semiconductor device. More particularly, it relates to a technology effectively applicable to the package structure of a semiconductor device (or a semiconductor integrated circuit device).
A semiconductor device including a plurality of semiconductor chips sealed in one package like a so-called SIP (system in package) is widely adopted as a technology for implementing a low-cost high-performance semiconductor device. Then, in order to implement the reduction in size of such a semiconductor device, generally, the structure in which over a semiconductor chip, another semiconductor chip is stacked is regarded as being effective. Thus, various studies have been made on the lamination structure of semiconductor chips.
For example, in Japanese Unexamined Patent Publication No. 2002-222913 (Patent Document 1), and its corresponding US patent No. 2002-96755 A (Patent Document 2), there is disclosed a technology of implementing multilayer die bonding whereby the flatness of each chip is ensured when mainly the semiconductor chips with the same size are stacked and mounted in a package. With this technology, after the completion of wire bonding of the lower chip, the upper chip having a die bonding adhesive layer at the bottom surface is pressed thereagainst from thereabove. As a result, the two chips are stacked one over another.
In Japanese Unexamined Patent Publication No. 2001-308262 (Patent Document 3), and its corresponding U.S. Pat. No. 6,545,365 (Patent Document 4), there is disclosed a technology of preventing a short circuit between a bonding wire and a chip after the completion of wire bonding of the lower chip when semiconductor chips are stacked and mounted in a package. With this technology, a sufficient amount of a die bonding resin is coated on the top surface of the lower chip, and an upper chip is disposed thereover. As a result, multilayer die bonding is implemented.
In Japanese Unexamined Patent Publication No. 2006-128169 (Patent Document 5), there is disclosed a technology of effectively preventing a short circuit between a wire and an upper chip, and a short circuit between wires when mainly the semiconductor chips with the same size are stacked and mounted in a package. With this technology, after the completion of wire bonding of the lower chip, the upper chip having a die bonding adhesive layer at the bottom surface is pressed thereagainst from thereabove. The die bonding adhesive layer includes an upper half layer into which a wire is less likely to penetrate, and a lower half layer into which a wire tends to penetrate.
In addition, for various objects, there is also disclosed a technology using bonding wires having different diameters as bonding wires coupled to a semiconductor chip in a package.
For example, in Japanese Unexamined Patent Publication No. 2006-84200 (Patent Document 6), there is disclosed a sensor device configured such that a sensor chip is stacked over a circuit chip via an adhesive. In this publication, there is disclosed a technology of setting the diameters of some of bonding wires for coupling a circuit chip and a sensor chip larger than those of other bonding wires in order to suppress fluctuations in sensor characteristics caused by the displacement of the sensor chip.
Whereas, in Japanese Unexamined Patent Publication No. 2008-192971 (Patent Document 7), there is disclosed a semiconductor device in which a memory chip is stacked over a mounting substrate, and a microcomputer chip is stacked over the memory chip. This publication discloses a technology of providing a semiconductor device which has implemented high integration and high reliability with a simple configuration. More specifically, there is disclosed a configuration in which the bonding wire for coupling the mounting substrate and the memory chip, and the bonding wire for coupling the memory chip and the microcomputer chip are larger in thickness than the bonding wire for coupling the microcomputer chip and the mounting substrate.
Further, in Japanese Unexamined Patent Publication No. 2010-267685 (Patent Document 8), there is disclosed a technology for reducing the size of a power module and providing a semiconductor device having a high mechanical reliability. In this publication, a plurality of switching elements are stored in one packaging case. The semiconductor device includes a first metal thin line and a second metal wire disposed generally in parallel to each other. The first metal thin line is larger in line diameter and longer than the second metal wire. However, in the semiconductor device disclosed in this publication, a plurality of semiconductor chips are not stacked, and are disposed side by side.